Publications

Found 68 results
Author Title Type [ Year(Asc)]
Filters: Author is Krste Asanović  [Clear All Filters]
2010
Tan, Z., Waterman A., Avižienis R., Lee Y., Cook H., Patterson D., et al. (2010).  RAMP Gold: An FPGA-Based Architecture Simulator for Multiprocessors.
Beamer, S., Sun C.., Kwon Y-J., Joshi A., Batten C., Stojanovic V., et al. (2010).  Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics. 129-140.
Colmenares, J. A., Bird S., Cook H., Pearce P., Zhu D.., Shalf J., et al. (2010).  Resource Management in the Tessellation Manycore OS.
2009
Batten, C., Joshi A., Orcutt J., Khilo A., Moss B., Holzwarth C., et al. (2009).  Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics. IEEE Micro. 29(4), 8-21.
Beamer, S., Asanović K., Batten C., Joshi A., & Stojanovic V. (2009).  Designing Multi-Socket Systems Using Silicon Photonics. 521-522.
Pan, H., Hindman B., & Asanović K. (2009).  Lithe: Enabling Efficient Composition of Parallel Libraries.
Stojanovic, V., Joshi A., Batten C., Kwon Y-J., & Asanović K. (2009).  Manycore Processor Networks with Monolithic Integrated CMOS Photonics.
Shalf, J., Asanović K., Patterson D., Keutzer K., Mattson T.., & Yelick K. (2009).  The Manycore Revolution: Will HPC Lead or Follow?. 40-49.
Jones, C.. G., Liu R., Meyerovich L.., Asanović K., & Bodik R. (2009).  Parallelizing the Web Browser.
Catanzaro, B., Kamil S., Lee Y., Asanović K., Demmel J., Keutzer K., et al. (2009).  SEJITS: Getting Poductivity AND Performance with Selective Embedded JIT Specialization.
Joshi, A., Batten C., Kwon Y-J., Beamer S., Shamim I., Asanović K., et al. (2009).  Silicon-Photonic Clos Networks for Global On-Chip Communication. 124-133.
Liu, R., Klues K., Bird S., Hofmeyr S., Asanović K., & Kubiatowicz J. D. (2009).  Tessellation: Space-Time Partitioning in a Manycore Client OS.
Asanović, K., Bodik R., Demmel J., Keaveny T., Keutzer K., Kubiatowicz J. D., et al. (2009).  A View of the Parallel Computing Landscape. Communications of the ACM. 52(10), 56-67.
Asanović, K., Bodik R., Demmel J., Keaveny T., Keutzer K., Kubiatowicz J. D., et al. (2009).  A View of the Parallel Computing Landscape. Communications of the ACM. 52(10), 56-67.
2008
Batten, C., Joshi A., Orcutt J., Khilo A., Moss B., Holzwarth C., et al. (2008).  Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics. 21-30.
Batten, C., Aoki H.., & Asanović K. (2008).  The Case for Malleable Stream Architectures.
Hampton, M.., & Asanović K. (2008).  Compiling for Vector-Thread Architectures. 205-215.
Tan, Z., Asanović K., & Patterson D. (2008).  An FPGA Host-Multithreaded Functional Model for SPARC v8.
Lee, J. W., Ng A.., & Asanović K. (2008).  Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks. 89-100.
Krashinsky, R., Batten C., & Asanović K. (2008).  Implementing the Scale Vector-Thread Processor. ACM Transactions on Design Automation of Electronic Systems. 13(3), 
Asanović, K., Bodik R., Demmel J., Keaveny T., Keutzer K., Kubiatowicz J. D., et al. (2008).  The Parallel Computing Laboratory at UC Berkeley: A Research Agenda Based on the Berkeley View.
2007
Heo, S., Krashinsky R., & Asanović K. (2007).  Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. IEEE Transactions on VLSI Systems. 15(9), 1060-1064.
Lee, J. W., King M.., & Asanović K. (2007).  Continual Hashing for Efficient Fine-Grain State Inconsistency Checking. 33-40.
Wawrzynek, J., Patterson D., Oskin M., Lu S-L., Kozyrakis C., Hoe J. C., et al. (2007).  RAMP: Research Accelerator for Multiple Processors. IEEE Micro. 27(2), 46-57.
Batten, C., Krashinsky R., & Asanović K. (2007).  Scale Control Processor Test-chip.

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