Publications

Found 68 results
Author Title Type [ Year(Asc)]
Filters: Author is Krste Asanović  [Clear All Filters]
2018
Asanović, K. (2018).  From T0 and CNS-1 to RISC-V and AI Hardware. 30 Years of Innovation: ICSI 30th Anniversary Celebration.
2013
Vo, H., Lee Y., Waterman A., & Asanović K. (2013).  A Case for OS-Friendly Hardware Accelerators.
Lee, Y., Krashinsky R., Grover V., Keckler S. W., & Asanović K. (2013).  Convergence and Scalarization for Data-Parallel Architectures.
Batten, C., Joshi A., Stojanovic V., & Asanović K. (2013).  Designing Chip-Level Nanophotonic Interconnection Networks.
Beamer, S., Buluç A., Asanović K., & Patterson D. (2013).  Distributed Memory Breadth-First Search Revisited: Enabling Bottom-Up Search.
Cook, H., Moretó M., Bird S., Dao K., Patterson D., & Asanović K. (2013).  A Hardware Evaluation of Cache Partitioning to Improve Utilization and Energy-Efficiency while Preserving Responsiveness.
Colmenares, J. A., Eads G., Hofmeyr S., Bird S., Moretó M., Chou D., et al. (2013).  Tessellation: Refactoring the OS around Explicit Resource Containers with Continuous Adaptation.
2012
Bachrach, J., Vo H., Richards B., Lee Y., Waterman A., Avižienis R., et al. (2012).  Chisel: Constructing Hardware in a Scala Embedded Language.
Tiwari, M., Mohan P., Osheroff A., Alkaff H., Shi E., Love E., et al. (2012).  Context-Centric Security.
Batten, C., Joshi A., Stojanovic V., & Asanović K. (2012).  Designing Chip-Level Nanophotonic Interconnection Networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2(2), 137-153.
Batten, C., Joshi A., Stojanovic V., & Asanović K. (2012).  Designing Chip-Level Nanophotonic Interconnection Networks. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2(2), 137-153.
Beamer, S., Asanović K., & Patterson D. (2012).  Direction-Optimizing Breadth-First Search.
Lee, J. W., Ng M. Cheuk, & Asanović K. (2012).  Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks. Journal of Parallel and Distributed Computing. 72(11), 1401-1411.
Maas, M., Reames P., Morlan J., Asanović K., Joseph A. D., & Kubiatowicz J. D. (2012).  GPUs: An Opportunity for Offloading Garbage Collection.
Zimmer, B., Toh S. Oon, Vo H., Lee Y., Thomas O., Asanović K., et al. (2012).  SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS. IEEE Transactions on Circuits and Systems-II. 59(12), 853-857.
2011
Tan, Z., Asanović K., & Patterson D. (2011).  Datacenter-Scale Network Research on FPGAs.
Lee, Y., Avižienis R., Bishara A.., Xia R.., Lockhart D.., Batten C., et al. (2011).  Exploring the Tradeoffs Between Programmability and Efficiency in Data-Parallel Accelerators. 129-140.
Colmenares, J. A., Saxton I., Battenberg E., Avižienis R., Peters N., Asanović K., et al. (2011).  Real-Time Musical Applications on an Experimental Operating System for Multi-Core Processors.
Waterman, A., Lee Y., Patterson D., & Asanović K. (2011).  The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA.
Beamer, S., Asanović K., & Patterson D. (2011).  Searching for a Parent Instead of Fighting Over Children: A Fast Breadth-First Search Implementation for Graph500.
2010
Tan, Z., Waterman A., Cook H., Bird S., Asanović K., & Patterson D. (2010).  A Case for FAME: FPGA Architecture Model Execution. 290-301.
Pan, H., Hindman B., & Asanović K. (2010).  Composing Parallel Software Efficiently with Lithe. 376-387.
Stojanovic, V., Joshi A., Batten C., Kwon Y-J., Beamer S., Chen S.., et al. (2010).  A Design-Space Exploration for CMOS Photonic Processor Networks.
Tan, Z., Asanović K., & Patterson D. (2010).  An FPGA-Based Simulator for Datacenter Networks.
Asanović, K., & Wittig R.. (2010).  Guest Editors' Introduction: Proceedings of the 21st Symposium on High Performance Chips (Hot Chips 21), Stanford, California. IEEE Micro. 30(2), 5-6.

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