Publications

Found 68 results
Author Title Type [ Year(Desc)]
Filters: Author is Krste Asanović  [Clear All Filters]
1990
Morgan, N., Asanović K., Kingsbury B., & Wawrzynek J. (1990).  Developments in Digital VLSI Design for Artificial Neural Networks.
1991
Asanović, K., & Morgan N. (1991).  Experimental Determination of Precision Requirements for Back-Propagation Training of Artificial Neural Networks.
Asanović, K., Kingsbury B., Morgan N., & Wawrzynek J. (1991).  HiPNeT-1: A Highly Pipelined Architecture for Neural Network Training.
Kingsbury, B., Irissou B., Asanović K., Wawrzynek J., & Morgan N. (1991).  Recent Work in VLSI Elements for Digital Implementations of Artificial Neural Networks.
Asanović, K., Beck J., Kingsbury B., Kohn P., Morgan N., & Wawrzynek J. (1991).  SPERT: A VLIW/SIMD Microprocessor for Artificial Neural Network Computations.
1993
Asanović, K., Beck J., Callahan T. J., Feldman J., Irissou B., Kingsbury B., et al. (1993).  CNS-1 Architecture Specification: A Connectionist Network Supercomputer.
Asanović, K., Beck J., Feldman J., Morgan N., & Wawrzynek J. (1993).  Designing a Connectionist Network Supercomputer. International Journal of Neural Systems.
1995
Wawrzynek, J., Asanović K., Kingsbury B., Beck J., Johnson D., & Morgan N. (1995).  SPERT-II: A Vector Microprocessor System and Its Application to Large Problems in Backpropagation Training. Proceedings of the Advances in Neural Information Processing Systems 8 Conference (NIPS 8). 619-625.
1996
Wawrzynek, J., Asanović K., Kingsbury B., Beck J., Johnson D., & Morgan N. (1996).  SPERT-II: A Vector Microprocessor System and Its Application to Large Problems in Backpropagation Training. IEEE Computer. 29(3), 79-86.
Asanović, K., & Beck J. (1996).  T0 Engineering Data.
Asanović, K., & Johnson D. (1996).  Torrent Architecture Manual.
1998
Bilmes, J. A., Asanović K., Chin C-W., & Demmel J. (1998).  The PHiPAC v1.0 Matrix-Multiply Distribution..
Asanović, K., Beck J., Johnson D., Kingsbury B., Morgan N., & Wawrzynek J. (1998).  Training Neural Networks with SPERT-II. 345-364.
Asanović, K. (1998).  Vector processing system with multi-operation, run-time configurable pipelines.
2006
Paxson, V., Asanović K., Dharmapurikar S., Lockwood J.., Pang R., Sommer R., et al. (2006).  Rethinking Hardware Support for Network Analysis and Intrusion Prevention. Proceedings of the First USENIX Workshop on Hot Topics in Security (HotSec '06).
2007
Heo, S., Krashinsky R., & Asanović K. (2007).  Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. IEEE Transactions on VLSI Systems. 15(9), 1060-1064.
Lee, J. W., King M.., & Asanović K. (2007).  Continual Hashing for Efficient Fine-Grain State Inconsistency Checking. 33-40.
Wawrzynek, J., Patterson D., Oskin M., Lu S-L., Kozyrakis C., Hoe J. C., et al. (2007).  RAMP: Research Accelerator for Multiple Processors. IEEE Micro. 27(2), 46-57.
Batten, C., Krashinsky R., & Asanović K. (2007).  Scale Control Processor Test-chip.
Krashinsky, R., Batten C., & Asanović K. (2007).  The Scale Vector-Thread Processor.
Asanović, K., & Witchel E.. (2007).  System and technique for fine-grained computer memory protection.
Asanović, K. (2007).  Transactors for Parallel Hardware and Software Co-design. Proceedings of the IEEE International High Level Design Validation and Test Workshop 2007 (HLDVT-2007). 140-142.
2008
Batten, C., Joshi A., Orcutt J., Khilo A., Moss B., Holzwarth C., et al. (2008).  Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics. 21-30.
Batten, C., Aoki H.., & Asanović K. (2008).  The Case for Malleable Stream Architectures.
Hampton, M.., & Asanović K. (2008).  Compiling for Vector-Thread Architectures. 205-215.

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