Publications

Found 18 results
Author Title Type [ Year(Desc)]
Filters: Author is John Wawrzynek  [Clear All Filters]
1990
Morgan, N., Asanović K., Kingsbury B., & Wawrzynek J. (1990).  Developments in Digital VLSI Design for Artificial Neural Networks.
1991
Asanović, K., Kingsbury B., Morgan N., & Wawrzynek J. (1991).  HiPNeT-1: A Highly Pipelined Architecture for Neural Network Training.
Kingsbury, B., Irissou B., Asanović K., Wawrzynek J., & Morgan N. (1991).  Recent Work in VLSI Elements for Digital Implementations of Artificial Neural Networks.
Asanović, K., Beck J., Kingsbury B., Kohn P., Morgan N., & Wawrzynek J. (1991).  SPERT: A VLIW/SIMD Microprocessor for Artificial Neural Network Computations.
1993
Asanović, K., Beck J., Callahan T. J., Feldman J., Irissou B., Kingsbury B., et al. (1993).  CNS-1 Architecture Specification: A Connectionist Network Supercomputer.
Asanović, K., Beck J., Feldman J., Morgan N., & Wawrzynek J. (1993).  Designing a Connectionist Network Supercomputer. International Journal of Neural Systems.
1995
Wawrzynek, J., Asanović K., Kingsbury B., Beck J., Johnson D., & Morgan N. (1995).  SPERT-II: A Vector Microprocessor System and Its Application to Large Problems in Backpropagation Training. Proceedings of the Advances in Neural Information Processing Systems 8 Conference (NIPS 8). 619-625.
1996
Wawrzynek, J., Asanović K., Kingsbury B., Beck J., Johnson D., & Morgan N. (1996).  SPERT-II: A Vector Microprocessor System and Its Application to Large Problems in Backpropagation Training. IEEE Computer. 29(3), 79-86.
1998
Chu, M., Weaver N., Sulimma K., DeHon A., & Wawrzynek J. (1998).  Object Oriented Circuit Generators in Java. Proceedings of the IEEE Symposium on Field Programmable Custom Computing Machines (FCCM).
Asanović, K., Beck J., Johnson D., Kingsbury B., Morgan N., & Wawrzynek J. (1998).  Training Neural Networks with SPERT-II. 345-364.
2000
Weaver, N., & Wawrzynek J. (2000).  A Comparison of the AES Candidates Amenability to FPGA Implementation.
2003
Weaver, N., Markovskiy Y., Patel Y., & Wawrzynek J. (2003).  Post Placement C-Slow Retiming for the Xilinx Virtex FPGA.
2004
Weaver, N., Hauser J., & Wawrzynek J. (2004).  The SFRA: A Corner-Turn FPGA Architecture. Proceedings of the 12th ACM International Symposium on Field Programmable Gate Arrays (FPGA 2004). 3-12.
2007
Wawrzynek, J., Patterson D., Oskin M., Lu S-L., Kozyrakis C., Hoe J. C., et al. (2007).  RAMP: Research Accelerator for Multiple Processors. IEEE Micro. 27(2), 46-57.
2008
Asanović, K., Bodik R., Demmel J., Keaveny T., Keutzer K., Kubiatowicz J. D., et al. (2008).  The Parallel Computing Laboratory at UC Berkeley: A Research Agenda Based on the Berkeley View.
2009
Asanović, K., Bodik R., Demmel J., Keaveny T., Keutzer K., Kubiatowicz J. D., et al. (2009).  A View of the Parallel Computing Landscape. Communications of the ACM. 52(10), 56-67.
Asanović, K., Bodik R., Demmel J., Keaveny T., Keutzer K., Kubiatowicz J. D., et al. (2009).  A View of the Parallel Computing Landscape. Communications of the ACM. 52(10), 56-67.
2012
Bachrach, J., Vo H., Richards B., Lee Y., Waterman A., Avižienis R., et al. (2012).  Chisel: Constructing Hardware in a Scala Embedded Language.